1. Field of the Invention
The present invention relates to a semiconductor device having multilayer wiring, and more particularly to a method of forming interconnections between an upper wiring layer and a lower wiring layer.
2. Description of the Related Art
FIG. 14 shows a partial sectional view of a conventional semiconductor device having a lower conductive layer or wiring layer including a first conductive line or wire 61, an inter-layer dielectric film 62 with a through hole 63, and an upper conductive layer or wiring layer including a second conductive line or wire 64 that is connected to the lower-layer wire 61 by a metal plug filling the through hole 63. The through hole 63 has a depth d, radius r, and diameter 2r. 
The multilayer wiring structure shown in FIG. 14 is fabricated as follows. First, a layer of metal is deposited on the entire surface of the device and patterned by photolithography and etching to form a lower-layer pattern of conductive lines 61. Next, the inter-layer dielectric film 62 is deposited on the entire surface and planarized by chemical-mechanical polishing (CMP). The inter-layer dielectric film 62 comprises a dielectric material such as silicate glass. The inter-layer dielectric film 62 is then etched to create through holes 63 at positions where the lower-layer conductive lines 61 will be connected to upper-layer conductive lines 64, and the through holes 62 are filled with metal. Another layer of metal is then deposited on the entire surface and patterned by photolithography and etching to create the upper-layer conductive lines 64.
As semiconductor device geometries have shrunk, so has the diameter (2r) of the through holes, and their aspect ratio (d/xcfx80r2) has increased. As a result, it has become difficult to assure the stable formation of a resist pattern for the small-diameter through holes in the photolithographic process, and to assure that the through holes will be etched to a constant depth during the etching process. The result is unreliable connections between the different wiring layers of a semiconductor device with multilayer wiring. The problem of the formation of a reliable connection structure for multilayer wiring has hindered progress toward devices with still smaller geometries.
A further problem is that if the depth d of the through holes is reduced as their diameter is reduced, the reduced spacing between wiring layers increases the parasitic capacitance of the wiring. The limiting dimensions for the stable formation of interconnections between different wiring layers in conventional semiconductor devices have been, for example, a through-hole diameter of one-fifth of a micrometer (2r=0.2 xcexcm) and a through-hole depth of one-half of a micrometer (d=0.5 xcexcm).
An object of the present invention is accordingly to provide a semiconductor device with a multilayer wiring interconnection structure that permits smaller device geometries.
Another object of the invention is to provide a fabrication method for such a semiconductor device.
The invented semiconductor device includes a first conductive layer and a second conductive layer. To connect a conductive line or pattern in the first conductive layer to a conductive line or pattern in the second conductive layer, a pair of conductive members or conductors are formed between the two conductive layers, both conductive members having heights less than the separation between the conductive layers. One conductive member makes contact with or is unitary with the conductive line or pattern in the lower conductive layer; the other conductive member makes contact with or is unitary with the conductive line or pattern in the upper conductive layer. The two conductive members extend for different distances in at least one direction parallel to the conductive layers. The two conductive members make mutual contact, thereby establishing an electrical path between the two conductive lines. One conductive member may be slotted to receive the other conductive member.
In one fabrication method for the invented semiconductor device, after a lower conductive layer is formed and patterned, a first dielectric film is deposited, covering the lower conductive layer. The first dielectric film is patterned to form a first hole extending to a conductive line or pattern in the lower conductive layer, and the first hole is filled with a conductive material to form a first conductive member or conductor. A second dielectric film is then deposited on the first dielectric film, and patterned to form a second hole extending to the first conductive member. The second hole is filled with a conductive material to form a second conductive member or conductor making contact with the first conductive member or conductor, and an upper conductive layer is formed on the second dielectric film. The upper conductive layer includes a conductive line or pattern making contact with the second conductive member.
In this method, the second conductive member and the upper conductive layer may be formed in a single step, by depositing a layer of conductive material that covers the second dielectric film and fills the second hole, then patterning this layer of conductive material to form the upper conductive layer. The second conductive member, disposed in the second hole, is unitary with a conductive line or pattern in the upper conductive layer.
Alternatively, the upper conductive layer may be formed by depositing a third dielectric film, patterning the third dielectric film to form trenches, and filling the trenches with a conductive material. The conductive material may be copper.
Similarly, the lower conductive layer may be formed by depositing a dielectric film, patterning the dielectric film to form trenches, and filling the trenches with a conductive material such as copper.
In another fabrication method for the invented semiconductor device, the lower conductive layer is formed in a two-step process that also forms the first conductive member or conductor. Specifically, a conductive film is patterned to form a conductive pattern. A coating of photoresist is applied, covering the conductive pattern, and the coating is patterned by photolithography to leave a mask that masks part of the conductive pattern. The exposed part of the conductive pattern is then etched to reduce its height. The part of the conductive pattern that is not etched because it is below the level at which etching is stopped becomes the lower conductive layer. A masked part of the conductive pattern remaining above this level becomes the first conductive member, which is unitary with the lower conductive layer. The second conductive member and the upper conductive layer are then formed substantially as described above, by depositing a dielectric film, forming a hole in the dielectric film extending to the first conductive member, filling the hole with a conductive material, and forming a conductive layer on the dielectric film.
Either fabrication method may by adapted to form a slot in the first conductive member to receive the second conductive member. For example, after the hole for the second conductive member has been formed, the first conductive member may be etched to create such a slot.
Needless to say, either fabrication method may be adapted to form a plurality of first conductive members and a plurality of second conductive members.
The invention enables the wiring dimensions of a semiconductor device to be reduced by reducing the widths of the conductive members without requiring an equal reduction of the lengths of the conductive members. Specifically, a conductive member having an elongated shape such as a rectangular bar shape can be made narrow enough to permit very fine, closely-spaced conductive lines, while still being long enough to ensure that the conductive member is reliably formed. Furthermore, if an electrical path between two conductive layers is created by a conductor having the form of an elongated bar meeting a conductor having the form of a plug, the hole for the plug-shaped conductor can be shallow enough to ensure reliable formation of the plug-shaped conductor, while the additional height of the bar-shaped conductor permits sufficient separation between the two conductive layers to avoid problems caused by parasitic capacitance.